The is built around the high-performance STM32F205RCT6
microcontroller, which serves as the core processing unit for managing USB-to-JTAG/SWD communication . This hardware revision significantly improved upon its predecessors by introducing high-speed USB 2.0 capabilities and enhanced level-shifting for target board compatibility. jlink v9 schematic
The architecture is designed to provide high-speed debugging with speeds reaching up to and 15 MHz for SWD . Go to product viewer dialog for this item. jlink v9 schematic