Providing the mechanical interface to probers or handlers. SmarTest Software Environment
Precise voltage levels are critical for CMOS logic. The manual details how to set VIHcap V sub cap I cap H end-sub VILcap V sub cap I cap L end-sub VOHcap V sub cap O cap H end-sub VOLcap V sub cap O cap L end-sub for various drive and receive modes. verigy 93k tester manual
The 93k platform is designed around a scalable architecture that allows for "per-pin" resources. Unlike traditional testers that share resources across multiple pins, the 93k provides dedicated timing, levels, and pattern memory for each channel. This ensures that complex System-on-Chip (SoC) devices can be tested with maximum precision. Providing the mechanical interface to probers or handlers
💡 Always maintain a "Golden Device." If a test fails across multiple units, run the Golden Device to determine if the issue lies with the tester hardware or the test program itself. The 93k platform is designed around a scalable
A standard test flow in the 93k environment follows a specific hierarchy outlined in the manual: